1. Field of the Invention
This invention relates to integrated circuits and more particularly to input buffer circuits at an external interface of integrated circuits that will receive digital signals from external circuitry, buffer the digital signals, and convert the digital signals to voltages level acceptable to internal circuitry within the integrated circuits.
2. Description of Related Art
The design of input buffer circuits for integrated circuits is well known in the art as shown in U.S. Pat. No. 4,475,050 (Noufer), U.S. Pat. No. 5,304,867 (Morris) and U.S. Pat. No. 5,355,033 (Jang). The input buffer is used to accept an input signal that will comply to the electrical characteristics for logic technologies such as transistor-transistor logic (TTL), Low Voltage TTL (LVTTL), Stub Series Terminated Logic (SSTL), and Gunning Transceiver Logic (GTL). The electrical characteristics for these logic technologies are often different from the electrical characteristics of the internal circuitry of the integrated circuits.
The input buffer should be simple in design, have minimal time delay, consume low power, and be highly tolerant to external electrical noise. Additionally the operating characteristics of the input buffer should vary minimally to variations in semiconductor processing parameters, power supply voltage, and temperature.
The standard input buffers of Complementary Metal Oxide Semiconductor (CMOS) integrated circuits are usually either a simple CMOS inverter that may or may not incorporate hysteresis (a Schmitt trigger) as shown in FIG. 1 or a differential amplifier as shown in FIG. 2. The CMOS inverter as shown in FIG. 1 will have a trip point or threshold where the voltage level of the input signal will cause the output to change from the voltage level of a first logic state (0) to the voltage level of a second logic state (1) or from the second logic state (1) to the first logic state (0). The trip point can be modified by the appropriate design of the transistors within the input buffer so that the trip point will correspond as nearly as possible to the midpoint of the possible voltage swing of the input signal.
The CMOS inverter circuit of FIG. 1 is generally the faster approach because the input controls both the NMOS and PMOS transistors by forcing one to a non-conducting state while forcing the other to a conducting state. The effective circuit amplification of this technique is very large. The trip point of the CMOS inverter of FIG. 1 is strongly dependent upon the power supply voltage source and the processing parameters. The variations of the power supply voltage source and the processing parameters will effectively vary the trip point of the CMOS inverter by nearly 0.8V. While this range is satisfactory for logic technologies such as LVTTL, it is not acceptable for such technologies as SSTL.
The differential amplifier input buffer of FIG. 2 will compare the voltage level of the input signals to that of a reference voltage Vref. If the voltage of the input signals transits between a voltage greater than the reference voltage Vref and a voltage less than the reference voltage Vref, the output will transit between the first logic state (0) and the second logic state (1). Since the reference voltage Vref can be precisely designed to be insensitive to variations in semiconductor processing parameters, power supply voltage, and temperature, the trip point can be precisely controlled.
Referring now to FIG. 1 for a more detailed description of a CMOS inverter incorporating a Schmitt trigger. The above described input signal is applied to the input terminal IN.sub.ext. The input terminal IN.sub.ext is generally the input pad of a semiconductor chip and is connected to the external circuitry that will be the source of the input signal. The N-channel metal oxide semiconductor (NMOS) transistors N.sub.1 and N.sub.2 and the P-channel metal oxide semiconductor (PMOS) transistors P.sub.2 and P.sub.3 are configured for the CMOS inverter. The gates of the NMOS transistors N.sub.1 and N.sub.2 and the PMOS transistors P.sub.2 and P.sub.3 are connected to the input terminal IN.sub.ext. The PMOS transistor P.sub.1 is used to activate and deactivate the CMOS inverter. An enable signal at the ENABLE terminal is connected to the gate of the PMOS transistor P.sub.1. If the enable signal is at the first logic state (0) it will cause the PMOS transistor P.sub.1 to conduct and the NMOS transistor N.sub.3 to cease conduction thus activating the CMOS inverter. However, if the enable signal is at the second logic state (1), it will cause the PMOS transistor P.sub.1 to cease conduction and the NMOS transistor N.sub.3 to conduct thus deactivating the CMOS inverter and bringing the output to the first logic state (0).
When the CMOS inverter is activated and the input signal begins to transit from a low voltage level or the first logic state (0) to a high voltage level or the second logic state (1), the NMOS transistors N.sub.1 and N.sub.2 begin to conduct and the PMOS transistors P.sub.2 and P.sub.3 begin to cease conduction. Once the input signal reaches the trip point, the NMOS transistors N.sub.1 and N.sub.2 are in equal conduction with the PMOS transistors P.sub.2 and P.sub.3 and the output is near mid-range. The input signal continues to the second logic state (1). As the loading capacitance attached to the output terminal OUT.sub.int is discharged through NMOS transistors N.sub.1 and N.sub.2, the voltage level at the output terminal OUT.sub.int will approach the voltage level of the low supply voltage source. Conversely, when the input signal begins to transit from a high voltage level or the first logic state (1) to the low voltage level or the second logic state (0), NMOS transistors N.sub.1 and N.sub.2 begin to cease conduction and the PMOS transistors P.sub.2 and P.sub.3 begin to conduct. As the input signal traverses the trip point, the NMOS transistors N.sub.1 and N.sub.2 become equal in conduction with the PMOS transistors P.sub.2 and P.sub.3. The input signal continues to the first logic state (0) The loading capacitance at the output terminal OUT.sub.int is now charged to the voltage level of the high supply voltage source through the PMOS transistors P.sub.2 and P.sub.3.
The trip point can be modified to provide hysteresis or a variation in the level of the trip points for the input signal going from the first logic state (0) to the second logic state (1) versus that of the input signal going from the second logic state (1) to the first logic state (0). The hysteresis is established by either the NMOS transistors N.sub.4 or the PMOS transistors P.sub.4, which may be optionally added to the circuit to adjust the hysteresis as needed.
When the input signal at the input terminal IN.sub.ext is at the second logic state (1) and the output signal at the output terminal OUT.sub.int is at the first logic state (0), the PMOS transistor P.sub.4 is in full conduction (the gate to source voltage of PMOS transistor P.sub.4 V.sub.gs is equal to the negative high supply voltage). As the input signal IN.sub.ext traverses from the second logic state (1) to the first logic state (0), The NMOS transistors N.sub.1 and N.sub.2 begin to conduct so there is current in the drain to source path of the series chain of transistors P.sub.1, P.sub.2, P.sub.3, N.sub.1, and N.sub.2. Since the PMOS transistor P.sub.4 is fully conducting, the common node to the PMOS transistors P.sub.2, P.sub.3, and P.sub.4 is essentially connected to the low supply voltage source. This common node is the source of the PMOS transistor P.sub.3 and consequently the PMOS transistor P.sub.3 is held in a non-conducting state. As the input signal continues to fall toward the first logic state (0), the PMOS transistor P.sub.2 begins to conduct harder and begins to raise the common node to the PMOS transistors P.sub.2, P.sub.3, and P.sub.4 from the low supply voltage level toward the high supply voltage level. The ratio of the sizes of the PMOS transistors P.sub.2 and P.sub.4 is such that PMOS transistor P.sub.3 is conducting when the input signal has reached the midrange of the signal swing (about 1/2 the high supply voltage level). As soon as the PMOS transistor P.sub.3 is in full conduction, the output signal at the output terminal OUT.sub.int begins to rise from the first logic state (0) to the second logic state (1). At this time the PMOS transistor P.sub.4 begins to cease conduction and the PMOS transistor P.sub.3 conducts harder. This will cause positive feedback, thus causing the output signal to rise more rapidly to the second logic state (1). Because to the action of the PMOS transistor P.sub.4, the input signal had to transition farther from the second logic state (1) to the first logic state (0) than if the PMOS transistor P.sub.4 had not been present, that is the trip point of the buffer was at a lower value for the second logic state (1) to the first logic state (0) transition than for the first logic state (0) to the second logic state (1) transition. The ratio of the geometries of the PMOS transistors P.sub.2 and P.sub.4 controls the level of the hysteresis.
The NMOS transistor N.sub.4 can optionally be added for total symmetry and adjustability of the hysteresis. When the input signal at the input terminal IN.sub.ext is at the first logic state (0) and the output signal at the output terminal OUT.sub.int is at the second logic state (1), the NMOS transistor N.sub.4 is in full conduction (the gate to source voltage of PMOS transistor N.sub.4 V.sub.gs is equal to the low supply voltage level). As the input signal IN.sub.ext traverses from the first logic state (0) to the second logic state (1), The NMOS transistors N.sub.1 and N.sub.2 begin to conduct so the current in the drain to source path of the series chain of transistors P.sub.1, P.sub.2, P.sub.3, N.sub.1, and N.sub.2 begins to increase. Since the NMOS transistor N.sub.4 is fully conducting, the common node to the NMOS transistors N.sub.2, N.sub.1, and N.sub.4 is essentially connected to the high supply voltage source. This common node is the source of the NMOS transistor N.sub.1 and consequently the NMOS transistor N.sub.1 is held off. As the input signal continues to rise toward the second logic state (1), the NMOS transistor N.sub.2 begins to conduct faster and begins to bring the common node to the NMOS transistors N.sub.2, N.sub.1, and N.sub.4 from the high supply voltage level toward the low supply voltage level. The ratio of the sizes of the NMOS transistors N.sub.2 and N.sub.4 is such that NMOS transistor N.sub.1 is conducting when the input signal has reached the midrange of the signal swing (about 1/2 the high supply voltage level). As soon as the NMOS transistor N.sub.1 is conducting, the output signal at the output terminal OUT.sub.int begins to fall from the second logic state (1) to the first logic state (0). At this time the NMOS transistor N.sub.4 begins to cease conduction and the NMOS transistor N.sub.1 to conduct harder. This will cause positive feedback, thus causing the output signal to fall more rapidly to the first logic state (0). Because to the action of the NMOS transistor N.sub.4, the input signal had to transition farther from the first logic state (0) to the second logic state (1) than if the NMOS transistor N.sub.4 had not been present, that is the trip point of the buffer was at a lower value for the first logic state (0) to the second logic state (1) transition than for the second logic state (1) to the first logic state (0) transition. The ratio of the geometries of the NMOS transistors N.sub.2 and N.sub.4 controls the level of the hysteresis.
To understand the operation of a differential input buffer, refer now to FIG. 2. The ratio of the geometry of the PMOS transistor P.sub.1 to that of the NMOS transistor N.sub.3 is equal to the ratio of the geometry of the PMOS transistor P.sub.2 to that of the NMOS transistor N.sub.4 (P.sub.1 :N.sub.3 ::P.sub.2 :N.sub.4) The reference voltage source Vref is coupled through the NMOS transistor N.sub.1 to the gate of the NMOS transistor N.sub.3, while the input signal is coupled through the NMOS transistor N.sub.2 to the gate of the NMOS transistor N.sub.4. The reference voltage source Vref forces the NMOS transistor N.sub.3 into conduction and establishes a bias point for the gate of the PMOS transistor P.sub.1. The ratio of the geometries for the PMOS transistor P.sub.1 to the NMOS transistor N.sub.3 is chosen such that the bias point is in the midrange between the high supply and the low supply. The common connection of the gates of the PMOS transistors P.sub.1 and P.sub.2 transfer this bias point to the section of the circuit containing the PMOS transistor P.sub.2 and the NMOS transistor N.sub.4. When the input signal at the input terminal IN.sub.ext is equal to the level of the reference voltage source Vref, the output terminal OUT.sub.int is at the bias point. This establishes a tight relationship between the level of the reference voltage source and the trip point of the buffer. If the input signal at the input terminal IN.sub.ext is traversing between first logic state (0) and the second logic state (1), the output signal at the output terminal OUT.sub.int will switch at the bias point established by the reference voltage source Vref.
The NMOS transistors N.sub.1 and N.sub.2 are to insure that any noise present at the voltage reference source Vref and the input terminal IN.sub.ext become as common mode as is possible. The NMOS transistors N.sub.1 and N.sub.2 are also decoupled to the high supply voltage source to some degree.
An enable signal at the ENABLE terminal is connected to the gate of the PMOS transistor P.sub.3. If the enable signal is at the first logic state (0) it will cause the PMOS transistor P.sub.1 thus activating the CMOS inverter. However, if the enable signal is at the second logic state (1), it will cause the PMOS transistor P.sub.1 to cease conduction thus deactivating the CMOS inverter.
The PMOS transistor P.sub.4 is connected in parallel with the PMOS transistor P.sub.2. The gate of the PMOS transistor P.sub.4 is connected to the output of the inverter I.sub.1 which is the output terminal OUT.sub.int. The PMOS transistor P.sub.4 provides feedback to create hysteresis by effectively changing the ratio of the geometries of the PMOS transistor P.sub.2 to that of the NMOS transistor N.sub.4 as the circuit is operating.